EON Express 6 GS/s digitizer PCIe

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EON Express, 12 bit, 6 GS/s, 1 Ch,  1.75 GHz BW, PCIe

  • 1 Ch 12 bit Analog input
  • Signle Ch 6 GS/s  Sampling rate
  • Software Selectable Sampling Rates, 1 kS/s - 6 GS/s
  • 1.75 GHz Bandwidth
  • 2 GS (4 GB) memory, expandable to 4 GS (8 GB)
  • Real-Time FPGA/DSP Functions
  • 4 GB/s sustanable data streaming
  • DC Coupling, 50 Ω Inputs (AC coupling optional)
  • Input range ±100 mV to ± 5V, software selectable
  • External/Reference Clock In & Clock Out
  • External Trigger In/Out with Advanced Triggering
  • Timestaping data capability
  • Multiboard Synchronization capability
  • PCIe Gen 3.0 x8 Interface Card
  • Driver for Windows 10/8/7 and Linux
  • GaGeScope PC Oscilloscope Software
  • SDK for C/C#, LabVIEW and MATLAB

EON Express, 12 bit, 6 GS/s, 1 Ch, 1.75 GHz BW, PCIe

Analog Input Front End

The EON Express is available in two models: a single channel model supporting a maximum A/D sampling rate up to 6 GS/s or a two channel model supporting a maximum A/D sampling rate up to 3 GS/s per channel. For the two channel model, ADC data can be captured in either dual channel or single channel mode.

The analog input bandwidth is 1.75 GHz with ±0.5 dB flatness to 1.25 GHz for both models. The input channels are fixed for DC-coupling with fixed 50 Ω input impedance. Onboard auto-calibration provides DC accuracy of ±0.5%. This wide 1.75 GHz bandwidth is especially useful for RF based applications by enabling direct RF sampling of wider band signals.

ADC Clock Circuit

The EON Express utilizes an onboard fixed master crystal oscillator as the primary internal clock source for the ADCs combined with clock control to effectively produce 27 software selectable A/D sampling rates ranging from 1 kS/s to 6 GS/s with a rate accuracy of ±1 Part Per Million (PPM).

Acquisition Memory

The EON Express includes 2 GS (4 GB) of onboard acquisition sample memory that can be optionally expanded to a maximum of 4 GS (8 GB). The onboard acquisition memory size is shared and equally divided among all active input channels (1 or 2) when acquiring data to onboard memory.


Advanced triggering operations include Simple, Complex, Windowed, and Multi-channel Boolean ORed.

Simple triggering uses a single trigger source from any input channel, external trigger, or software with software controls for trigger level and trigger slope (positive or negative). Each time the selected trigger source signal crosses the set trigger level with set trigger slope, a digital trigger is generated to initiate acquisition.

In order to avoid triggering on noise, the EON Express features a trigger sensitivity value of ±5% of Full Scale Input Range (FSIR) of the trigger source. This value specifies the minimum amount by which the trigger signal must swing through the trigger level in order to cause a trigger event.


Timestamping is a feature used to determine the arrival time of waveform trigger events and is most useful when used in Multiple Record Mode. The digitizer has a 44-bit on-board numerical counter. The clock source for the counter may be selected as the digitizer sampling clock or a fixed on-board clock source. The value of the timestamp counter can be reset to zero at the beginning of each acquisition sequence or can be alternatively reset from software at some referenced time.

During an acquisition and upon each trigger event, the current output value of the timestamping counter is latched and is stored in onboard memory as a footer to the current record. After acquisition, the timestamp value associated with each acquired record may be downloaded. When dividing the timestamp value by the known counter source frequency, the occurrence time of each trigger event is obtained.

Multi-Card Systems

Multiple EON Express cards can work together either within a single system or across multiple systems in three possible configurations: Independent, Synchronized Cascade, or Synchronized Split.

More Information

EON Express Specification

Model # :CSE123G2CSE126G1
# of Input Channels : 2 1
Vertical A/D Resolution : 12-bit
Max. Rate per Channel : 3 GS/s 6 GS/s
Bandwidth 1.75 GHz
Connector SMA
Impedance 50 Ω
Couplin DC (AC is Optional)
Analog bandwidth DC (50 Ω) = DC to 1.5 GHz
Rates per Channel(software selectable)
3 GS/s, 1.5 GS/s, 1 GS/s, 750 MS/s, 500 MS/s, 375 MS/s, 250 MS/s, 187.5 MS/s, 125 MS/s, 75 MS/s, 50 MS/s, 30 MS/s, 20 MS/s, 10 MS/s, 4 MS/s, 2 MS/s, 1 MS/s, 500 kS/s, 200 kS/s, 100 kS/s, 50 kS/s, 20 kS/s, 10 kS/s, 5 kS/s, 2 kS/s, 1 kS/s 6 GS/s, 3 GS/s, 1.5 GS/s, 1 GS/s, 750 MS/s, 500 MS/s, 375 MS/s, 250 MS/s, 187.5 MS/s, 125 MS/s, 75 MS/s, 50 MS/s, 30 MS/s, 20 MS/s, 10 MS/s, 4 MS/s, 2 MS/s, 1 MS/s, 500 kS/s, 200 kS/s, 100 kS/s, 50 kS/s, 20 kS/s, 10 kS/s, 5 kS/s, 2 kS/s, 1 kS/s
Voltage Ranges
software selectable
±100 mV, ±200 mV, ±500 mV, ±1 V, ±2 V, ±5 V
DC User Offseet
software selectable
Spans Full Scale Input Range (FSIR)
Flatness : Within ±0.5 dB of ideal response to 1.25 GHz
Rate Accuracy : ±1 part-per-million (0° to 50° C ambient)
Absolute Max.Input ±6 V (over-voltage protection included)
Interchannel Skew < 50 picoseconds
Interchannel Skew Jitter < 3 picoseconds RMA
Shared between active channels (1 or 2) Standard Size : 2 GS (4 GB)
Optional Sizes : 4 GS (8 GB)
Architecture : Dual Port
Data Streaming : Yes
Trigerring Engines : 2 per Channel, 1 for External Trigger
Source : Any Input Channel, External Trigger or Software
Input Combination : All Combinations of Sources Logically OR’ed
Slope : Positive or Negative (software selectable)
Sensitivity : ±5% of Full Scale Input Range of Trigger Source. This implies that signal amplitude must be at least 5% of full scale to cause a trigger to occur. Smaller signals are rejected as noise.
External Trigger Connector : SMA
Impedance : ≈ 1k Ω
Coupling : DC
Bandwidth : >100 MHz
Voltage Range : 5 V TTL
Trigger Out Connector : SMA
Impedance : 50 Ω
Amplitude : 0 – TTL
CLOCK IN Connector : SMA
Signal Level : Min 200 mV RMS, Max 500 mV RMS
Impedance : 50 Ω
Coupling: DC
Duty Cycle: 50% ±5%
Input modes: External Clock or 10 MHz Reference Clock
External Clock Mode Input Rates: 200 MHz to 3 GHz
Variable/Inactive External Clock Mode: inactive external clock, particularly useful for OCT applications
CLOCK OUT Connector : SMA
Signal Level : ±1.2 mV
Impedance : 50 Ω
Duty Cycle: 50% ±5%
Output Modes : 10 MHz Reference Clock
Frequency : 10 MHz
Pre-Trigger Data Up to FPGA memory size
Timing Resolution One Sample Clock Cycle
Independent Each card operates independently within the system.
Synchronized Cascade Each card operates together as a group by cascading the trigger signal via the Trigger Out
Synchronized Split Each card operates together as a group by splitting the trigger signal to each card’s Trigger In using an RF power splitter (not a BNC Tee)
DIMENSIONS Size : Single Slot, Full Height, Full Length
POWER CONSUMPTION 25 Watts (typical)
PC SYSTEM REQUIREMENTS PCI Express (PCIe) Slot : 1 Free Full-Height Full-Length
PCIe Gen1, Gen2 or Gen3, x8 or x16 Slot
Operating System Windows 10/8/7 (32-bit/64-bit),
Linux – Requires SDK for C/C#
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