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XU-AWG
XU-AWG
Two 16-bit RF DACs Up to 5 GSPS and UltraScale FPGA
- AD9162 DAC supports enhanced 2nd and 3rd Nyquist and “Frequency Doubling” 2x Modes
- Single-Ended AC-Coupled Outputs with Programmable DC Bias
- Digital Inverse Sinc Filter
- 48-Bit NCO
- Fixed Deterministic Latency
- Interpolation Filters: 1x (bypass mode), 2x, 3x, 4x, 6x, 8x,12x,16x, 24x
- Internal or External Reference Clock
- Internal TI LMK04828 or LMK04821 Master Reference PLL with Zero Delay Mode
- Individually Delay Controlled Reference Clock to Each DAC Slave PLL and FPGA
- Advanced Triggering Input Registered to JESD204B Reference Clock
- External Clock and Trigger Inputs
- Reference Clock Output
- XCKU060 Xilinx Kintex Ultrascale FPGA
- 4GB DDR4 DRAM in 2 Banks Each with 64- Bit Interface
- VHDL FrameWork Logic
- Windows/Linux Drivers
- C++ DevKit
- High Speed Arbitrary Waveform Generation
- RADAR and Jammers
- Electronic Warfare
- IP Development
- Instrumentation and Automated Test Equipment
XU-AWG
Two 16-bit RF DACs Up to 5 GSPS and UltraScale FPGA
The XU-AWG is an XMC module with two 8-lane high speed serial links: one on XMC connector P15 and one on P16. These links can support several protocols (up to 8-lane PCIe, Aurora or user defined). The XU-AWG features two AC-coupled single-ended DAC outputs with programmable DC bias. The Analog Devices AD9162 high-speed/high performance DACs employ synchronization support, interpolation, fixed latency and unique output circuits providing improved frequency synthesis in the 2nd and 3rd Nyquist zones.
A Xilinx Kintex Ultrascale XCKU060 FPGA with 4GB DDR4 RAM memory provides a high-performance DSP core for demanding applications such as RADAR and wireless IF generation. The close integration of the analog front end, memory, and host interface with the FPGA enables real-time signal processing.
The XU-AWG XMC module couples a powerful multi-channel PCIe DMA architecture with a high performance 8 lane PCI Express link connected to the carrier. PCIe link speeds up to Gen3 are supported; however, the actual PCIe link performance depends on the XMC carrier and the host system.
The XU-AWG FPGA design can be fully customized using VHDL and the FrameWork Logic Devkit. Xilinx JESD204B IP license, purchased separately from Xilinx, is required for logic development.
A software development kit for host development includes C++ libraries and 64-bit drivers for Windows and Linux. An application demonstrating the module’s features, including streaming DAC samples from disk, is provided.
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